Erm... A shitton of tools. You roughly write and validate an HLL description, translate it to gates or more generally/correctly library cells and then place them and route the connecting wires. GDS-II has everything at an exact place, from that they make wafer masks. But each stage is many tools and it's not fully independent considerations.

Or you can use Chuck Moore's famous 500 lines of Forth to produce a chip for 180 nm that can't access DRAM and go on about everyone doing it wrong.